CHAPTER
1
INTRODUCTION
In general, this
chapter will explain about the identification of the Development of Universal
Asynchronous Receiver/ Transmitter using Verilog HDL. At the beginning of this
chapter, some introduction of this project will be implemented to get the full
understanding about this project. The project background will be explained in
this chapter to clarify the basic idea about this project. In addition the
project statement, objective of the project, scope of project / limitation and
summary of chapter are also been explained to make it more clearly about this
project.
A Universal
Asynchronous Receiver/Transmitter is a piece of computer hardware that
translates data between parallel and serial forms. UARTs are commonly used in
conjunction with communication standards such as EIA, RS-232, RS-422 or RS-485.
The universal designation indicates that the data format and transmission
speeds are configurable. The electric signaling levels and methods such as
differential signaling are handled by a driver circuit external to the UART. A
UART is usually an individual (or part of an) integrated circuit used for
serial communications over a computer or peripheral device serial port. UARTs
are now commonly included in microcontrollers. A dual UART, or DUART, combines
two UARTs into a single chip. Many modern ICs now come with a UART that can
also communicate synchronously these devices are called USARTs (Universal Synchronous/Asynchronous
Receiver/ Transmitter).
The Universal
Asynchronous Receiver/Transmitter (UART) takes bytes of data and transmits the
individual bits in a sequential fashion. At the destination, a second UART
re-assembles the bits into complete bytes. Each UART contains a shift register,
which is the fundamental method of conversion between serial and parallel
forms. Serial transmission of digital information (bits) through a single wire
or other medium is less costly than parallel transmission through multiple
wires. The UART usually does not directly generate or receive the external
signals used between different items of equipment. Separate interface devices
are used to convert the logic level signals of the UART to and from the
external signaling levels. External signals may be of many different forms.
Examples of standards for voltage signaling are RS-232, RS-422 andRS-485 from
the EIA. Historically, current (in current loops) was used in telegraph
circuits. Some signaling schemes do not use electrical wires. Examples of such
are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port
Profile (SPP). Some signaling schemes use modulation of a carrier signal (with
or without wires). Examples are modulation of audio signals with phone line
modems, RF modulation with data radios, and the DC-LIN for power line
communication.
1.1
PROJECT
BACKGROUND
Abbreviation for Universal
Asynchronous Receiver-Transmitter, UART is a chip used to manage computer
serial ports, disk drive interrupts, screen refresh cycles, and any other
device that requires timing. With a serial port transmission, the UART converts
the bytes into serial bits and transmits those bits through an asynchronous
transmission, stripping out the start and stop bits for each character. Below
is a listing of various UART chips. The 16550 chip series is the most commonly
used UART. The Universal Asynchronous Receiver Transmitter (UART) is a popular
and widely-used device for data communication in the field of
telecommunication. A UART is the microchip with programming that controls a
computer's interface to its attached serial devices. Specifically, it provides
the computer with the RS-232 Data Terminal Equipment (Data Terminal Equipment )
interface so that it can communicate to and exchange data with modems and other
serial devices. More advanced UARTs provide some amount of buffer of data so that
the computer and serial devices data streams remain coordinated. The most
recent UART, the 16550, has a 16-byte buffer that can get filled before the
computer's processor needs to handle the data. The original UART was the 8250.
If you purchase an internal modem today, it probably includes a 16550 UART
(although you should ask when you buy it). According to modem manufacturer
robotics, external modems do not include a UART. For an older computer, we as
user want to add an internal 16550 to get the most out of the external modem.
A Universal Asynchronous
Receiver/Transmitter, is a piece of computer hardware that translates data
between parallel and serial forms. UARTs are commonly used in conjunction with
communication standards such as EIA, RS-232, RS-422 or RS-485. The universal
designation indicates that the data format and transmission speeds are
configurable. The electric signaling levels and methods such as differential
signaling are handled by a driver circuit external to the UART. A UART is
usually an individual (or part of an) integrated circuit used for serial
communications over a computer or peripheral device serial port. UARTs are now
commonly included in microcontrollers. A dual UART, or DUART, combines two
UARTs into a single chip. Many modern ICs now come with a UART that can also
communicate synchronously these devices are called USARTs (Universal
Synchronous/ Asynchronous Receiver/ Transmitter).
The Universal Asynchronous Receiver/Transmitter (UART) takes
bytes of data and transmits the individual bits in a sequential fashion. At the
destination, a second UART re-assembles the bits into complete bytes. Each UART
contains a shift register, which is the fundamental method of conversion
between serial and parallel forms. Serial transmission of digital information
(bits) through a single wire or other medium is less costly than parallel
transmission through multiple wires. The UART usually does not directly
generate or receive the external signals used between different items of
equipment. Separate interface devices are used to convert the logic level
signals of the UART to and from the external signaling levels. External signals
may be of many different forms. Examples of standards for voltage signaling are
RS-232, RS-422 andRS-485 from the EIA. Historically, current (in current loops)
was used in telegraph circuits. Some signaling schemes do not use electrical
wires. Examples of such are optical fiber, IrDA (infrared), and (wireless)
Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use
modulation of a carrier signal (with or without wires). Examples are modulation
of audio signals with phone line modems, RF modulation with data radios, and
the DC-LIN for power line communication.
1.2 PROJECT
STATEMENT
The purpose of
this project is to develop UART controller interface. A Universal Asynchronous
Receiver/ Transmitter (UART) is a hardware that translates data between
parallel and serial forms. UART is used for serial communications over a
computer or peripheral device serial port. UART are commonly used in
conjunction with communication standards such as RS-232 or RS-422. Uart is
commonly included in microcontrollers. This project will be implemented using
Verilog HDL. Then it will programmed into Altera DE2 board using for proof of
concept.
1.2.1 Receiver
All
operations of the UART hardware are controlled by a clock signal which runs at
a multiple of the data rate. For example, each data bit may be as long as 16
clock pulses. The receiver tests the state of the incoming signal on each clock
pulse, looking for the beginning of the start bit. If the apparent start bit
lasts at least one-half of the bit time, it is valid and signals the start of a
new character. If not, the spurious pulse is ignored. After waiting a further
bit time, the state of the line is again sampled and the resulting level
clocked into a shift register. After the required number of bit periods for the
character length (5 to 8 bits, typically) have elapsed, the contents of the shift
register is made available (in parallel fashion) to the receiving system. The
UART will set a flag indicating new data is available, and may also generate a
processor interrupt to request that the host processor transfers the
received data.
The
best UARTs "resynchronize" on each change of the data line that is
more than a half-bit wide. In this way, they reliably receive when the
transmitter is sending at a slightly different speed than the receiver. (This
is the normal case, because communicating units usually have no shared timing
system apart from the communication signal.) Simplistic UARTs may merely detect
the falling edge of the start bit, and then read the center of each expected
data bit. A simple UART can work well if the data rates are close enough that
the stop bits are sampled reliably.
It
is a standard feature for a UART to store the most recent character while
receiving the next. This "double buffering" gives a receiving
computer an entire character transmission time to fetch a received character.
Many UARTs have a small first-in, first-out FIFO buffer memory
between the receiver shift register and the host system interface. This allows
the host processor even more time to handle an interrupt from the UART and
prevents loss of received data at high rates.
1.2.2 Transmitter
Transmission
operation is simpler since it is under the control of the transmitting system.
As soon as data is deposited in the shift register after completion of the
previous character, the UART hardware generates a start bit, shifts the
required number of data bits out to the line, generates and appends the parity
bit (if used), and appends the stop bits. Since transmission of a single
character may take a long time relative to CPU speeds, the UART will maintain a
flag showing busy status so that the host system does not deposit a new
character for transmission until the previous one has been completed; this may
also be done with an interrupt. Since full-duplex operation requires characters
to be sent and received at the same time, UARTs use two different shift
registers for transmitted characters and received characters.
1.3 PROBLEM
STATEMENT
This project
attempts to develop an UART interface using Verilog HDL. In telecommunications,
RS-232 (Recommended Standard 232) is a standard for serial binary single-ended
data and control signals connecting between a DTE (Data Terminal Equipment) and
a DCE (Data Circuit-terminating Equipment). It is commonly used in computer
serial ports. A similar ITU-T standard is V.24.
When developing
or troubleshooting systems using RS-232, close examination of hardware signals
can be important to find problems. A serial line analyzer is a device similar
to a logic analyzer but specialized for RS-232's voltage levels, connectors,
and, where used, clock signals. The serial line analyzer can collect, store,
and display the data and control signals, allowing developers to view them in
detail. Some simply display the signals as waveforms; more elaborate versions
include the ability to decode characters in ASCII or other common codes and to
interpret common protocols used over RS-232 such as SDLC, HDLC, DDCMP, and
X.25. Serial line analyzers are available as standalone units, as software and
interface cables for general-purpose logic analyzers, and as programs that run
in common personal computers.
1.4 OBJECTIVES
OF THE PROJECT
The objectives of the proposed
project, Development of Universal Asynchronous Receiver/ Transmitter are;
- To design a serial
asynchronous receiver and transmitter communication with standard I/O
serial devices.
- To design a UART
that can be prototyping Altera DE2, then testing and debugging the
prototype in system.
- To analyze the
features of UART technology and make comparison with other existing UART
technology.
- To implement the
asynchronous receiver-transmitter in Altera DE2 board to achieve fast
prototyping and design verification.
- To learn and
expertise using Verilog HDL and Altera DE2.
1.5
SCOPE
OF PROJECT/LIMITATION
In order to
achieve the objective of this project, there are several scope had been
outlined. The application of RS-232 has extended far beyond the original
purpose of interconnecting a terminal with a modem, successor standards have
been developed to address the limitations. The scope of this project includes:
1.5.1 Large
Voltage Swings
The
need for higher voltage swings in applications such as test-and-measurement
instruments is constantly increasing, but the power supplies impose limitations
on the operational amplifier rails make the high-voltage need a challenge for
designers. We must deliver high-voltage swings to a load without increasing the
voltage levels of the power supplies of the operational amplifier. In other
words, for example, we produce a ±16V or greater signal swing across the load
using only ±15V power supplies. The circuit uses a fully differential amplifier
to offer an answer to this problem. Fully differential amplifiers enable you to
deliver an output-voltage swing beyond the rails into the load. One of the
common problems in working with operational amplifiers is the limit that the
power-supply rails impose. The standard since the days of analog computers has
been ±15V. Analog computers are gone, but their legacy remains in the power-supply
voltages. These voltages find widespread use in transducer interfaces and
applications in which voltage swing and dynamic range are of primary
importance.
1.5.2 Single-ended
Signaling
Single-ended signaling is the simplest
and most commonly used method of transmitting electrical
signals over wires. One wire carries a varying voltage that
represents the signal, while the other wire is connected to a reference
voltage, usually ground. The main alternative to single-ended signaling is
called differential signaling.
There is also the historic alternative of ground return, rarely used
today. Single ended signaling is less expensive to implement than differential,
but it lacks the ability to reject noise caused by differences in ground voltage
level between transmitting and receiving circuits and induction picked up on
the signal wire. The main advantage of single-ended over differential signaling
is that fewer wires are needed to transmit multiple signals. If there are n signals,
then there are n+1 wires - one for each signal and one for ground.
Differential signaling uses at least 2n wires. A disadvantage of
single-ended signaling is that the return currents for all the
signals share the same conductor even if separate ground wires are used, the
grounds are inevitably connected together at each end and this can sometimes
cause interference crosstalk between the signals.
1.5.3 Propogation
Delays
In electronics, digital
circuits and digital electronics, the propagation delay, or gate
delay, is the length of time which starts when the input to a logic
gate becomes stable and valid, to the time that the output of that logic
gate is stable and valid. Often this refers to the time required for the output
to reach from 10% to 90% of its final output level when the input changes.
Reducing gate delays in digital circuits allows them to process data at a
faster rate and improve overall performance.
The difference in propagation delays of logic
elements is the major contributor to glitches in asynchronous
circuits as a result of race conditions.
The principle of logical
effort utilizes propagation delays to compare designs implementing the
same logical statement. Propagation delay increases with operating
temperature, marginal supply voltage as well as an increased output load
capacitance. The latter is the largest contributor to the increase of
propagation delay. If the output of a logic gate is connected to a long trace
or used to drive many other gates high fanout the propagation delay increases
substantially.
1.5.4 Multi-drop
Connection
A multidrop bus (MDB) is
a computer bus in which all components are connected to the
electrical circuit. A process of arbitration determines which device sends
information at any point. The other devices listen for the data they are
intended to receive. Multidrop buses have the advantage of simplicity and
extensibility. However, modern SDRAM chips exemplify the problem
of electrical impedance discontinuity. Fully Buffered
DIMM is an alternative approach to connecting
multiple DRAM modules to a memory controller. Since 2000, multidrop
standards such as PCI and Parallel ATA are increasingly
being replaced by point-to-point systems such as PCI
Express and SATA.
1.5.5 Asymmetrical
definitions
Asymmetrical
definitions of the two ends of the link make the assignment of the role of a
newly developed device problematic; the designer must decide on either a
DTE-like or DCE-like interface and which connector pin assignments to use.
Limitation of the project is at
market segment. The usages of the project are mostly for lecturer or laboratory
examiner only. It needs electronics knowledge to determine the data.
1.6
SUMMARY
OF THE CHAPTER
This chapter
focuses on the introduction to this project and the objectives of this project.
This chapter briefly explained about the introduction of this project, project
background, project statement, objective and scope of project. In conclusion,
this chapter gives more details about this project.
CHAPTER
2
LITERATURE
REVIEW
2.1
HISTORY
Some early telegraph schemes used
variable-length pulses (as in Morse code) and rotating clockwork
mechanisms to transmit alphabetic characters. The first UART-like devices
(with fixed-length pulses) were rotating mechanical switches (commutators). Various character
codes using 5, 6, 7, or 8 data bits became common in teleprinters and
later as computer peripherals. Gordon Bell designed the UART for
the PDP series of computers. The teletypewriter made an excellent
general-purpose I/O device for a small computer. To reduce costs, including
wiring and back-plane costs, these computers also pioneered flow control
using XON and XOFF characters rather than hardware wires.
Western Digital made the first single-chip UART
WD1402A around 1971; this was an early example of a medium scale
integrated circuit. Another popular chip was a SCN2651 from the Signetics
2650 family.
An example of an early 1980s UART was
the National Semiconductor 8250. In the 1990s, newer UARTs were
developed with on-chip buffers. This allowed higher transmission speed without
data loss and without requiring such frequent attention from the computer. For
example, the popular National Semiconductor 16550 has a 16
byte FIFO, and spawned many variants, including the 16C550, 16C650, 16C750, and 16C850.
Depending on the manufacturer, different terms are used
to identify devices that perform the UART functions. Intel called
their 8251 device a "Programmable Communication
Interface". MOS Technology 6551 was known under the name
"Asynchronous Communications Interface Adapter" (ACIA). The term
"Serial Communications Interface" (SCI) was first used
at Motorola around 1975 to refer to their start-stop asynchronous
serial interface device, which others were calling a UART.
2.1.1 RS232 port.
RS-232 was first
introduced in 1962 by the Radio
Sector of the EIA.The original DTEs were electromechanical teletypewriters, and the original DCEs
were (usually) modems. When electronic terminals (smart and dumb)
began to be used, they were often designed to be interchangeable with
teletypewriters, and so supported RS-232. The C revision of the standard was
issued in 1969 in part to accommodate the electrical characteristics of these
devices.
Since the requirements of devices
such as computers, printers, test instruments, POS terminals and so on were not
considered by the standard, designers implementing an RS-232 compatible
interface on their equipment often interpreted the requirements
idiosyncratically. Common problems were non-standard pin assignment of circuits
on connectors, and incorrect or missing control signals. The lack of adherence
to the standards produced a thriving industry of breakout boxes, patch boxes,
test equipment, books, and other aids for the connection of disparate
equipment. A common deviation from the standard was to drive the signals at a
reduced voltage. Some manufacturers therefore built transmitters that supplied
+5 V and -5 V and labeled them as "RS-232 compatible".
Later personal computers (and
other devices) started to make use of the standard so that they could connect
to existing equipment. For many years, an RS-232-compatible port was a standard
feature for serial communications, such as modem connections, on many computers. It
remained in widespread use into the late 1990s. In personal computer
peripherals, it has largely been supplanted by other interface standards, such
as USB. RS-232 is still used to connect older designs of peripherals,
industrial equipment (such as PLCs),console ports and special
purpose equipment.
The standard has been renamed
several times during its history as the sponsoring organization changed its
name, and has been variously known as EIA RS-232, EIA 232, and most recently as
TIA 232. The standard continued to be revised and updated by the Electronic Industries Alliance and since 1988 by
the Telecommunications Industry Association (TIA).Revision C
was issued in a document dated August 1969. Revision D was issued in 1986. The
current revision is TIA-232-F
Interface Between Data Terminal Equipment and Data Circuit-Terminating
Equipment Employing Serial Binary Data Interchange, issued in 1997.
Changes since Revision C have been in timing and details intended to improve
harmonization with the CCITT standard V.24, but
equipment built to the current standard will interoperate with older versions.
Related ITU-T standards include
V.24 (circuit identification) and V.28 (signal voltage and timing
characteristics).
In revison D of EIA-232, the
D-subminiature connector was formally included as part of the standard (it was
only referenced in the appendix of RS 232 C). The voltage range was extended to
+/- 25 volts, and the circuit capacitance limit was expressly stated as 2500
pF. Revision E of EIA 232 introduced a new, smaller, standard D-shell 26-pin
"Alt A" connector, and made other changes to improve compatibility
with CCITT standards V.24, V.28 and ISO 2110.
2.1.2 Altera
DE2 board.
Altera
Corporation is a Silicon
Valley manufacturer of PLDs,
reconfigurable complex digital circuits. The company released its first PLD in
1984.Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the
MAX series CPLDs (Complex programmable
logic devices),the HardCopy
series ASICs and
Quartus II design software.
2.1.3 FPGA
The Stratix series FPGAs are the
company's largest, highest bandwidth devices, with up to 1.1 million logic
elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of
serial switching capability, up to 1,840 GMACs of signal-processing
performance, and up to 7 x72 DDR3 memory interfaces at 800 MHz. Cyclone
series FPGAs and SoC FPGAs are the company's lowest cost, lowest power FPGAs,
with variants offering integrated transceivers up to 5 Gbit/s. In between these
two device families are Arria series FPGAs and SoC FPGAs, which provide a
balance of performance, power, and cost for mid-range applications such as
remote radio heads, video conferencing equipment, and wireline access equipment.
Arria FPGAs have integrated transceivers up to 10 Gbit/s. In December 2012, the
company announced that they are shipping their first 28nm SoC FPGA
devices.According to Altera, fully depleted silicon on insulator (FDSOI) chip
manufacturing process is benefitial for FPGAs.
2.1.4 ASIC
Altera offers a design
flow based on HardCopy ASICs, which transitions the FPGA design, once
finalized, to a form which is not alterable. This design flow reduces design
security risks as well as costs for higher volume production. Design engineers
can prototype their designs in Stratix series FPGAs, and then migrate these
designs to HardCopy ASICs when they're ready for volume production.
The
unique design flow makes hardware/software co-design and co-verification
possible. The flow has been benchmarked to deliver systems to market 9 to 12
months faster, on average, than with standard-cell solutions. Design engineers
can employ a single RTL, set of intellectual property (IP) cores, and Quartus
II design software for both FPGA and ASIC implementations. Altera's HardCopy
Design Center manages test insertion.
2.1.5 Verilog
HDL
In 1970''s
when IC fabrication was in the primitive stages then designers were doing the
digital design using schematics. But then the design complexity has risen
exponentially. So in order to keep up with the designing complex circuits,
electronics and electrical engineers were looking for some alternative way of
defining the hardware. Thus born is the (Hardware description Language) HDL''s.
There are many HDLs now and the popular HDLs are VHDL, Verilog and
systemC.
These HDL''s are different
from the usual computer languages from the way it is executed. Computer
languages like C, C++ are sequentially executed whereas HDL''s are executed
concurrently. By concurrent we refer to the way the statements are executed. Hardwares
are not executed sequentially like a c program instead many blocks of the
design work in parallel, so concurrent execution is a must. VHDL is a project
of DARPA and Verilog HDL is from the Gateway design Automation (GDA). Cadence
acquired GDA and released the language in the public domain and thus the
popularity of the language grew rapidly. Thus many fabrication companies around
the world supported verilog libraries thus making even more popular.
There are many simulators available on the internet and the best for a student is Modelsim from Mentor Graphics. Verilog has many advantages over VHDL, one of them being the similarity with C language. In order to build a good command over the design we build, it is important digital design fundamentals are proper. Once this is over then rest is learning the syntax of the language and make a succesful design. A good reference book to verilog language can be "Verilog HDL by Samir Palnitkar", "HDL design by Douglas J Smith", Verilog HDL by Phil Moorby(Original verilog HDL architect with GDA) and the Language reference manual(LRM). Verilog is a verilfication language and hence have rich capabilities for testing. PLI(programming Language Interface) which gives the added flexibility in testing and verification for the code written in C and then to be integrated with HDL code. Another flexible feature is UDP which stands for User Defined Primitives.
There are many simulators available on the internet and the best for a student is Modelsim from Mentor Graphics. Verilog has many advantages over VHDL, one of them being the similarity with C language. In order to build a good command over the design we build, it is important digital design fundamentals are proper. Once this is over then rest is learning the syntax of the language and make a succesful design. A good reference book to verilog language can be "Verilog HDL by Samir Palnitkar", "HDL design by Douglas J Smith", Verilog HDL by Phil Moorby(Original verilog HDL architect with GDA) and the Language reference manual(LRM). Verilog is a verilfication language and hence have rich capabilities for testing. PLI(programming Language Interface) which gives the added flexibility in testing and verification for the code written in C and then to be integrated with HDL code. Another flexible feature is UDP which stands for User Defined Primitives.
Verilog was the first modern hardware description
language to be invented. It was created by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this process was
"Automated Integrated Design Systems" (later renamed to Gateway
Design Automation in
1985) as a hardware modeling language. Gateway Design Automation was purchased
by Cadence
Design Systems in 1990.
Cadence now has full proprietary rights to Gateway's Verilog and the
Verilog-XL, the HDL-simulator that would become the de facto standard (of
Verilog logic simulators) for the next decade. Originally, Verilog was
intended to describe and allow simulation; only afterwards was support for
synthesis added.
2.2 Previous
Work
2.2.1 Embedded
System
The purpose of this study was to interface at all dedicated only to one task to complex graphical user interfaces that resemble modern computer desktop operating systems. Simple embedded devices use buttons, LEDs, graphic or character LCDs (for example popular HD44780 LCD) with a simple menu system. More sophisticated devices which use a graphical screen with touch sensing or screen-edge buttons provide flexibility while minimizing space used: the meaning of the buttons can change with the screen, and selection involves the natural behavior of pointing at what's desired. Handheld systems often have a screen with a "joystick button" for a pointing device.
Some systems provide user interface remotely with the help of a serial (e.g. RS-232, USB, I²C) or network (Ethernet) connection. This approach gives several advantages: extends the capabilities of embedded system, avoids the cost of a display, simplifies BSP, allows us to build rich user interface on the PC. A good example of this is the combination of an embedded web server running on an embedded device (such as an IP camera) or a network routers. The user interface is displayed in a web browser on a PC connected to the device, therefore needing no bespoke software to be installed.
An embedded system is a computer system designed for specific control functions within a larger system, often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of end-user needs. Embedded systems control many devices in common use today. Embedded systems contain processing cores that are either microcontrollers or digital signal processors (DSP). A processor is an important unit in the embedded system hardware. It is the heart of the embedded system.
The key characteristic, however, is being dedicated to handle a particular task. Since the embedded system is dedicated to specific tasks, design engineers can optimize it to reduce the size and cost of the product and increase the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale. Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, and largely complex systems like hybrid vehicles, MRI, and avionics. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure.
2.2.2 Development
Board: Wireless Transceiver
Figure
2.2.2a: Wireless Transceivers.
Features
·
Running
frequency: 915M,2.5K Frequency Step.
·
64 channels
setting, non-volatile on power off, Transmitting power: 7dBm
·
Receiving
sensitivity: -109dBm
·
Modulation
method: FSK
·
Receiving
method: Zero IF digital receiving
·
Airborne speed
rate: 300-19200bps
·
Serial port
speed rate:19200bps
·
Transmitting
current: 20-30mA(including MCU)
·
Receiving
current: 15-20mA(including MCU)
·
Standby current:
<1ua o:p="">1ua>
·
Running voltage:
2.8-3.3V
·
Communication
distance: 250-350m(Notes: the maximum communication distance correlates
with environment, antenna form and communication speed rate).
Transmit
Once
initialised, transmitting data is quite simple;
1.
Ensure TXR Busy
pin is HIGH (indicates the module is free to transmit - no incoming/outgoing
packets).
2.
Send UART data
to TXR RXD pin (that's right, data is sent to the RXD pin on the TXR).
3.
Wait for 15mS
(module will send data automatically after a 10mS delay - 15mS is the
recommended wait time).
·
Be sure to
connect the UART TX pin of the PIC to the RXD pin on the TXR module.
·
The TXR module
has a 63 byte transmit buffer. You can send 1 byte or 63 bytes - anything after
this will be ignored.
·
Once data is
sent to the TXR, the 15mS delay will initiate the transmit.
·
The TXR Busy pin
will go high for the duration of the transmit.
·
The TXR Busy pin
can drive loads upto 20mA. This allows an LED with series resistor to be
connected to it. The LED will flash when TX/RX wireless data.
Receiver
Even easier then transmitting, receiving goes like
this;
1.
Received
wireless data will be transmitted from the TXR TXD pin.
- Use the hardware UART module/library to ensure no lost/corrupt
data.
Program
Naturally, a program says a thousands words. Consider the following
TRANSMIT program. Program designed to operate with a 10Mhz external crystal.
Also, there is some initialisation code for the development board I made which
configures the MAX3223 interface - disregard if just using the TXR.
2.2.3 Wireless Temperature and
Humadity Sensor
Figure 2.2.3a: Wireless Temperature and Humadity Sensor
This project is based on the principle of Universal Asynchronous
Receiver/ Transmitter (UART) which The
temperature and humidity sensor used is an Sensirion SHT15 which I picked-up
from Futurelec. The datasheet claims accuracy of ±2.0%
for relative humidity measurements and ±0.4°C for temperature measurements. The
SHT15 gives 14bit temperature and 12bit humidity readings via a 2-wire serial
interface. Unfortunately the interface is not I2C compatible so I had to
write a Swordfish module to handle communications between the PIC and the sensor.
XBee RF modules are used to provide the
wireless link between the sensor and the base station. The XBee modules
are really easy to use they have an
integrated antenna and are ready to go straight out the box. Apply power,
feed serial data into the UART of one and it comes out the other without any
setting-up or tweaking. Multiple XBee modules can be linked together into a
Personal Area Network (PAN). Each module in the PAN has its own address
and messages can either be broadcast to all modules or addressed to a specific
one. The modules will ignore any messages which don’t come from within
the PAN. The PAN ID, module address and other settings are configured using AT
commands sent through the module’s UART. Swordfish module to handle
putting the XBee into AT Command Mode and setting / reading the control
parameters. The pins on the XBee
modules are 2mm pitch so they can’t be plugged directly into breadboard for
prototyping. Also, the modules are 3.3V parts which was a problem for me
as I’ve only got 5V PICs to hand. To get around these problems I used a
Droids breakout board. The board brings the pins out to a 2.54mm pitch
and also includes a 3.3V regulator to power the XBee from a 5V supply.
The XBee’s DataIn and
DataOut pins connect to the TX and RX pins of the PIC’s USART. As the
XBee is a 3.3V device, a voltage divider brings the 5V output of the PIC’s TX
pin down to a level which the XBee can handle. The RX pin on the PIC is
connected directly to the DataOut of the XBee. The only other connection
to the PIC is the XBee’s Sleep pin which is used to put it into a low power
mode between transmissions.
2.3 Present
Work
It is the recent
development of The Universal
Asynchronous Receiver/Transmitter (UART) controller is the key component of the
serial communications subsystem of a computer. The UART takes bytes of data and
transmits the individual bits in a sequential fashion. At the destination, a
second UART re-assembles the bits into complete bytes. Serial transmission is
commonly used with modems and for non-networked communication between
computers, terminals and other devices. There are two primary forms of serial
transmission: Synchronous and Asynchronous. Depending on the modes that are
supported by the hardware, the name of the communication sub-system will
usually include A if it supports Asynchronous communications and S if
it supports Synchronous communications.
2.4 Asynchronous
Serial Transmission
Asynchronous
transmission allows data to be transmitted without the sender having to send a
clock signal to the receiver. Instead, the sender and receiver must agree on
timing parameters in advance and special bits are added to each word which are
used to synchronize the sending and receiving units.
When
a word is given to the UART for Asynchronous transmissions, a bit called the
"Start Bit" is added to the beginning of each word that is to be
transmitted. The Start Bit is used to alert the receiver that a word of data is
about to be sent, and to force the clock in the receiver into synchronization
with the clock in the transmitter. These two clocks must be accurate enough to
not have the frequency drift by more than 10% during the transmission of the
remaining bits in the word. (This requirement was set in the days of mechanical
teleprinters and is easily met by modern electronic equipment.)
After
the Start Bit, the individual bits of the word of data are sent, with the Least
Significant Bit (LSB) being sent first. Each bit in the transmission is
transmitted for exactly the same amount of time as all of the other bits, and
the receiver “looks” at the wire at approximately halfway through the
period assigned to each bit to determine if the bit is a 1 or
a 0. For example, if it takes two seconds to send each bit, the receiver
will examine the signal to determine if it is a 1 or
a 0 after one second has passed, then it will wait two seconds and
then examine the value of the next bit, and so on. The sender does not know
when the receiver has “looked” at the value of the bit. The sender
only knows when the clock says to begin transmitting the next bit of the word.
When the entire data word has been sent, the transmitter may add a Parity Bit
that the transmitter generates. The Parity Bit may be used by the receiver to
perform simple error checking. Then at least one Stop Bit is sent by the
transmitter. When the receiver has received all of the bits in the data word,
it may check for the Parity Bits (both sender and receiver must agree on
whether a Parity Bit is to be used), and then the receiver looks for a Stop
Bit. If the Stop Bit does not appear when it is supposed to, the UART considers
the entire word to be garbled and will report a Framing Error to the host
processor when the data word is read. The usual cause of a Framing Error is
that the sender and receiver clocks were not running at the same speed, or that
the signal was interrupted. Regardless of whether the data was received
correctly or not, the UART automatically discards the Start, Parity and Stop
bits. If the sender and receiver are configured identically, these bits are not
passed to the host. If another word is ready for transmission, the Start Bit
for the new word can be sent as soon as the Stop Bit for the previous word has
been sent.
2.5 REVIEW
HISTORY
Modems for
personal computers that plug into a motherboard slot must also include the UART
function on the card. The original 8250 UART chip shipped with the IBM personal
computer had no on-chip buffering for received characters, which meant that
communications software performed poorly at speeds above 9600 bits/second,
especially if operating under a multitasking system or if handling interrupts
from disk controllers. High-speed modems used UARTs that were compatible with
the original chip but which included additional FIFO buffers, giving software
additional time to respond to incoming data.
A
look at the performance requirements at high bit rates shows why the 16, 32, 64
or 128 byte FIFO is a necessity. The Microsoft specification for a DOS system
requires that interrupts not be disabled for more than 1 millisecond at a time.
Some hard disk drives and video controllers violate this specification. 9600
bit/s will deliver a character approximately every millisecond, so a 1 byte
FIFO should be sufficient at this rate on a DOS system which meets the maximum
interrupt disable timing. Rates above this may receive a new character before
the old one has been fetched, and thus the old character will be lost. This is
referred to as an overrun error and results in one or more lost characters.
With error correcting modems, any lost characters will be retransmitted, but
retransmission slows the connection.
A
16 byte FIFO allows up to 16 characters to be received before the computer has
to service the interrupt. This increases the maximum bit rate the computer can
process reliably from 9600 to 153,000 bit/s if it has a 1 millisecond interrupt
dead time. A 32 byte FIFO increases the maximum rate to over 300,000 bit/s. A
second benefit to having a FIFO is that the computer only has to service about
8 to 12% as many interrupts, allowing more CPU time for updating the screen, or
doing other chores. Thus the computer's responses will improve as well.
2.6 SUMMARY OF THE CHAPTER
This review has introduced the technique
of Universal Asynchronous Receiver/ Transmitter and has demonstrated its great
potential for use in a wide range of communication. A main focus has been the
assessment of the data transmission system. In recent years there has been
interesting the technique, and driven by the demand for low cost, simple and
portable technology forth settings, the availability of low cost and small
semiconductor components, and the advancement of computer analysis techniques.
This design uses Verilog HDL as design
language to achieve the modules of UART. Using this software, Altera’s series
chip to complete simulation and test, the result may be stable and reliable.
The design has great flexibility, high integration with some reference value.
Especially in the field of electronic design, where technology has recently
become increasingly mature, this design shows great significance. This project
describes the architecture of UART that support various data word length,
parity selection and baud rates for serial transmission of data. Working
principle of this UART has been tested using simulator, which can be
implemented on Altera DE2.
The literature review describe about the
history of Development of Universal Asynchronous Receiver/Transmitter for
analysis to get an overview of project’s plan. The history is divided into two;
previous work and present work. For previous history, the time required is 4
months starting from January till April 2013. Meanwhile, for present history,
it briefly explained about the component listing and purchasing component
parts, which took about a months to complete.
CHAPTER
3
METHODOLOGY
3.1 INTRODUCTION
OF PROJECT’S METHODOLOGY
This chapter will discuss about the methodology of
this project. The methodology chapter explains the procedure of a researcher’s
academic studies. Methodology chapter are intended to be complete, detailed
reports of studies with the objective that any other researcher could replicate
the study exactly to determine if the same results would be obtained. This
chapter will explain more details about block diagram, hardware development and
software development.
3.2 BLOCK DIAGRAM
Figure
3.2a: System block diagram
3.2.1 EXPLANATION
Actually UART receives/sends data to
microprocessor/microcontroller through data bus. The remaining part of signal
handling of RS-232 is done by UART for example start bit, stop bit, and parity.
The following is the experimental
set up for serial communication form. Data from PIC / MPLAB software will be
received to RS-232 Transceiver. It modifies or converts signal into format
appropriate for efficient channel of transmission. Next it will implement using
Verilog HDL. Verilog is a verilfication language and hence have rich
capabilities for testing. PLI (Programming Language Interface) which gives the
added flexibility in testing and verification for the code written in C and
then to be integrated with HDL code. Hence, it will connect to UART Peripheral
connector which is physical medium through RS-232. Then it will programmed into
Altera DE2 board for proof of concept.
3.3
HARDWARE
AND DEVELOPMENT
3.3.1 THE ELECTRONIC PARTS
i.
Max 232 interfacing
ii.
RS 232 port
iii.
Altera DE2 board
3.3.1.1 Max 232 Interfacing Circuit
Figure 3.3.1.1a : Max
232 Schematic Diagram
The MAX232 is an
integrated circuit that converts signals from an RS-232 serial port to signals
suitable for use in TTL compatible digital logic circuits. The MAX232 is a dual
driver/receiver and typically converts the RX (receiver), TX (transmitter), CTS
and RTS signals. The later MAX232A is backwards compatible with the original
MAX232 but may operate at higher baud rates and can use smaller external
capacitors – 0.1 μF in place of the 1.0 μF capacitors used with the original
device. It is helpful to understand what occurs to the voltage levels. When a
MAX232 IC receives a TTL level to convert, it changes a TTL Logic 0 to between
+3 and +15 V, and changes TTL Logic 1 to between -3 to -15 V.
Figure
3.3.1.1b : Max 232 chip
Figure
3.3.1.1c : Max 232 functional diagram
3.3.1.2 RS232 port.
Below is the
pinout of a typical standard male 9-pin RS232 connector, this connector type is
also referred to as a DB9 connector.
A computer's
serial COM port (DTE) is usually a male port as shown below, and any peripheral
devices connect to this port usually has a female connector (DCE).
Figure 3.3.1.2a: RS232 Pin Configurations
The
main features of hardware and software are as follows :
Hardware:
Interface:
UART(RS232/RS422/TTL)
Data
rate: 1200~115200 BPS
Power
supply :3V or 6V
Receiving
Current:160mA
Transmitting
current:200mA(Peak
current 250mA)
Standby
current: 120mA
Software:
Verilog
HDL, Windows.
Network
Protocol: FPGAs, and
GPUs as coprocessors
Working
Environment Operation Temperature:-20C ~ 85C
Storage
Temperature:-40C ~
125C
Figure 3.3.1.3a: DE2
Development and Educational Board
The Altera DE2 Development and Education board was
designed by professors, for professors. It is an ideal vehicle for learning
about digital logic, computer organization, and FPGAs. Featuring an Altera
Cyclone II 2C35 FPGA, the DE2 board is designed for university and college
laboratory use. It is suitable for a wide range of exercises in courses on
digital logic and computer organization, from simple tasks that illustrate
fundamental concepts to advanced designs. Altera DE2 Development board as
follows:
Feature
|
Description
|
FPGA
|
·
Cyclone II EP2C35F672C6 with EPCS16 16-Mbit serial
configuration device
|
I/O Interfaces
|
·
Built-in USB-Blaster for FPGA configuration
·
Line In/Out, Microphone In (24-bit Audio CODEC)
·
Video Out (VGA 10-bit DAC)
·
Video In (NTSC/PAL/Multi-format)
·
RS232
·
Infrared port
·
PS/2 mouse or keyboard port
·
10/100 Ethernet
·
USB 2.0 (type A and type B)
·
Expansion headers (two 40-pin headers)
|
Memory
|
·
8 MB SDRAM, 512 KB SRAM, 4 MB Flash
·
SD memory card slot
|
Displays
|
·
Eight 7-segment displays
·
16 x 2 LCD display
|
Switches and LEDs
|
·
18 toggle switches
·
18 red LEDs
·
9 green LEDs
·
Four debounced pushbutton switches
|
Clocks
|
·
50 MHz clock
·
27 MHz clock
·
External SMA clock input
|
3.4
SOFTWARE AND DEVELOPMENT
This chapter
will discuss the information and reference about the software development for
each circuit part of this project. In order to develop the project, the
strategy must be thoroughly planned before starting to build it.
3.4.1
Verilog HDL Software
Figure 3.4.1a: Verilog HDL Lecture Note
3.4.2 Data Encoding
When
no data transmitted D remains high. To signal a start of new transmission D
goes low for 1 bit period, which is known as “Start bit”. After the Start Bit,
the individual bits of data are sent. Each bit in the transmission is
transmitted for exactly the same amount of time as all of the other bits. After
transmission of entire data has been sent then D again goes to high, the last
bit known as “Stop bit”. Transmission of next data can begin any time after
that.In our project we have “even parity” bit for parity check.
Test
Bench (Receiver and Transmitter): Receiver and
Transmitter are working independently.
Figure
3.4.2a: Verilog HDL Software Interface
3.4.3 Receiver
Receiver
takes data serially in RxD pin, and provides the parallel to the Data out pin.
UART receiver consists of RDR (Received Data Reg.) and controller. When the
UART detects start bit receiver reads and shifts 8 data bits serially into a
temporary register. When 8 data bits has been received and parity check passes
then after stop bit has been received controller transfers data from temporary
register to RDR and received signal goes high.
Receiver VHDL Model
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityuart_receiveris
Port(clk:inSTD_LOGIC;
rx:instd_logic;
reset :inSTD_LOGIC;
baud_tick:inSTD_LOGIC;
data_out:outSTD_LOGIC_VECTOR(7downto0);
received :outSTD_LOGIC;
count1:outstd_logic_vector(3downto0);
count2:outstd_logic_vector(2downto0)
);
enduart_receiver;
architecture Behavioral ofuart_receiveris
type state is(idle,startbit,databits,paritybit,stopbit);
signalstate_reg,next_state_reg: state;
signalcounter,next_count:std_logic_vector(3downto0);
signaldata_count,data_next_count:std_logic_vector(2downto0);
signalrec,next_rec:std_logic_vector(7downto0):="00000000";
signalparity:std_logic;
begin
process(clk, reset)
begin
if(reset='1')
then
state_reg<=idle;
counter<=(others=>'0');
data_count<=(others=>'0');
elsif(rising_edge(clk)AND reset='0')
then
state_reg<=next_state_reg;
counter<=next_count;
data_count<=data_next_count;
rec<=next_rec;
endif;
endprocess;
state_decode:process(state_reg,rx,counter,baud_tick)
begin
if(state_reg=idle)then
next_state_reg<=state_reg;
data_next_count<=data_count;
received<='0';
next_count<=counter;
next_rec<=rec;
if(rx= '0')then
next_state_reg<=startbit;
next_count<=(others=>'0');
next_rec<="00000000";
endif;
elsif(rising_edge(baud_tick))then
next_state_reg<=state_reg;
data_next_count<=data_count;
received<='0';
next_count<=counter;
next_rec<=rec;
if(state_reg=startbit)then
if(('0'&counter)=7)
then
next_state_reg<=databits;
next_count<=(others=>'0');
data_next_count<=(others=>'0');
else
next_count<=counter+1;
endif;
elsif(state_reg=databits)then
if(('0'&counter)=15)then
next_count<=(others=>'0');
next_rec<=(rx& rec(7downto1));
if(('0'&data_count)=7)then
next_state_reg<=paritybit;
else
data_next_count<=data_count+1;
endif;
else
next_count<=counter+1;
endif;
elsif(state_reg=paritybit)then
if(('0'&counter)=15)then
next_count<=(others=>'0');
next_state_reg<=stopbit;
if(not(parity=rx))then
next_rec<="01000101";
endif;
else
next_count<=counter+1;
endif;
elsif(state_reg=stopbit)then
if(('0'&counter)=10)
then
received<='1';
next_count<=counter+1;
elsif(('0'&counter)=15)then
next_state_reg<=idle;
else
next_count<=counter+1;
endif;
endif;
endif;
endprocess;
parity<=rec(7)xor rec(6)xor rec(5)xor rec(4)xor rec(3)xor rec(2)xor rec(1)xor rec(0);
data_out<=rec;
count1<=counter;
count2<=data_count;
end Behavioral;
3.4.4 Transmitter
Transmitter
takes parallel data and sends it serially on the TxD pin.The transmitter
consists of TDR (Transmit Data Register),TSR (Transmit Shift Register) and
controller. As load signal goes high transmitter transfers data from TDR to TSR
and outputs start bit “0” to the TxD pin then shifts TSR right eight times to
transmit 8 bits. When eight data bits
transmitted ,transmitter sends parity bit and
finally outputs stop bit”1” to the TxDpin and signal “transmitted” goes
high.
Transmitter VHDL Model
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
port(
clk:inSTD_LOGIC;
reset :inSTD_LOGIC;
load :inSTD_LOGIC;
baud_tick:inSTD_LOGIC;
din :instd_logic_vector(7downto0);
transmitted :outSTD_LOGIC;
TxD:outSTD_LOGIC;
count1:outstd_logic_vector(3downto0);
count2:outstd_logic_vector(2downto0)
);
end transmitter;
architecture archof transmitter is
type state is(idle,start,data,parity_s,stop);
signalstate_reg,state_next:state;
signalcount,count_next:std_logic_vector(3downto0);
signaldcount,dcount_next:std_logic_vector(2downto0);
signal TSR ,TSR_next:std_logic_vector(7downto0):="00000000";
signaltx,tx_next:std_logic;
signalparity:std_logic;
begin
process(clk, reset)
begin
if(reset='1')
then
state_reg<=idle;
count<=(others=>'0');
dcount<=(others=>'0');
TSR<=(others=>'0');
tx<='1';
elsif(rising_edge(clk)AND reset='0')
then
state_reg<=state_next;
count<=count_next;
dcount<=dcount_next;
TSR<=TSR_next;
tx<=tx_next;
endif;
endprocess;
state_decode:process(state_reg,baud_tick,tx,load,din)
begin
if(state_reg=idle)
then
state_next<=state_reg;
count_next<=count;
dcount_next<=dcount;
TSR_next<=TSR;
transmitted<='0';
tx_next<='1';
if(load = '1')
then
state_next<=start;
count_next<=(others=>'0');
TSR_next<=din;
endif;
elsif(rising_edge(baud_tick))
then
state_next<=state_reg;
count_next<=count;
dcount_next<=dcount;
TSR_next<=TSR;
tx_next<=tx;
transmitted<='0';
if(state_reg= start)
then
tx_next<=tx;
if(('0'&count)=15)
then
state_next<= data;
count_next<=(others=>'0');
dcount_next<=(others=>'0');
else
count_next<=count+1;
endif;
endif;
if(state_reg= data)
then
tx_next<=TSR(0);
if(count=15)
then
count_next<=(others=>'0');
TSR_next<= '0' &TSR(7downto1);
if(dcount=7)
then
state_next<=parity_s;
else
dcount_next<=dcount+1;
endif;
else
count_next<= count +1;
endif;
endif;
if(state_reg=parity_s)
then
tx_next<=parity;
if(count=15)
then
count_next<=(others=>'0');
state_next<= stop;
else
count_next<= count +1;
endif;
endif;
if(state_reg= stop)
then
tx_next<='1';
if(count=10)
then
transmitted<='1';
count_next<= count +1
elsif(count=15)
then
state_next<= idle;
else
count_next<= count +1;
endif;
endif;
endif;
endprocess;
count1 <=(count);
count2 <=dcount;
parity<=din(7)xor din(6)xor din(5)xor din(4)xor din(3)xor din(2)xordin(1)xor din(0);
TxD<=tx;
end arch;
3.5 SUMMARY OF THE CHAPTER
As
conclusion, might say the overall of the methodology had been discussed by
sharing the same ideas and combining the knowledge of the software and hardware
development. The hardware development is the most important element that
inclusive of block diagram, hardware prototype and their description. The block
diagram is explained about basic concept operation of Development of Universal
Asynchronous Receiver/ Transmitter using Verilog HDL.
For the software development, I am using Verilog HDL
software to communicate between the RS232 port with Altera DE2 board. This
software is one of important as the machine instructions or source code that
responsible to perform the desired task as required.
Last but not least, this chapter is very useful as the
guidance and it is also helpful to overview the whole project that will be
implemented in the future. Therefore it is very significant to discover the new
application design.
CHAPTER
4
RESULT
AND ANALYSIS
4.1 INTRODUCTION
This
chapter will explain the expected result of Development of Universal
Asynchronous Receiver / Transmitter Interface using Verilog HDL.
Transmitting and receiving UARTs must be set for the
same bit speed, character length, parity, and stop bits for proper operation.
The receiving UART may detect some mismatched settings and set a framing error
flag bit for the host system; in exceptional cases the receiving UART will
produce an erratic stream of mutilated characters and transfer them to the host
system.
Typical serial
ports used with personal computers connected to modems use eight data bits, no
parity, and one stop bit; for this configuration the number of ASCII characters
per second equals the bit rate divided by 10.
Some very
low-cost home computers or embedded systems dispensed with
a UART and used the CPU to sample the state of an input port or
directly manipulate an output port for data transmission. While very
CPU-intensive, since the CPU timing was critical, these schemes avoided the
purchase of a UART chip. The technique was known as a banging serial port.
4.1.1 The Electronic Circuit Analysis and Theory
Figure below
shows that the electronic circuit of Universal Asynchronous Receiver /
Transmitter using PIC 16F877A. The circuit contains of:
1. Pull down resistor
2. Oscillator
3. UART interface driver
4. PIC 16F877A chip
5. 4X3 push button keypad
The function of pull down resistor
is to pull current into the circuit and supply voltage to the PIC 16F877A to
make sure the circuit is on. Oscillator provides a good contribution of frequency
to make sure the noise in the circuit is at the minimum level. The ideal
frequency for this circuit is around 12MHz. UART interface driver is an
important component in this final year project. I need to calibrate the driver
so that it could be interface to Altera DE2 board. PIC 16F877A chip is a reader
for MPLAB IDE program code (microcontroller) whether I write my program have no
error and can run the program. While 4X3 push button keypad is to verify and
show that what I push at this keypad will appear at the Altera DE2 board.
Figure 4.1.1a : Electronic
circuit of Universal Asynchronous Receiver / Transmitter using PIC 16F877A
4.2 THE EXPECTED OUTPUT
Below is the
expected output for this final year project. The expected output including RTL
viewer, State Machine viewer and last but not least the most important UART
Verilog HDL code.
Figure 4.2a: RTL Viewer
From the RTL viewer we can see
reset, clock and start logic circuit, adder, or gates, bit counter, shift
register, baud rate counter and D flip flop. The systems has been used Quartus II 2011 as simulation
software. It was very important to develop and test such design before a
physical prototype is constructed.
Figure 4.2b : State
Machine Viewer
Figure 4.2c : UART
Verilog Code
This project has extremely difficult programming
code to interface it by using 2 different of programming software. However, I
am manage to success to run the program using Verilog HDL.
4.3 THE EXPECTED RESULT
The
figure below show what is the expected result from this Final Year Project.
This expected result including Successful compiling using MPLAB IDE software,
keypad compiling using MPLAB IDE software, RS 232 compiling using MPLAB IDE
software, UART main compiling using MPLAB IDE software and UART compiling using
MPLAB IDE software.
Figure 4.3a : Successful
compiling using MPLAB IDE software
Figure 4.3b : Keypad
compiling using MPLAB IDE software
This
part of coding I use switch_case method to perform the program. I have to
design the keypad exactly as the Electronic circuit of Universal Asynchronous
Receiver / Transmitter using PIC 16F877A to make sure there is no error while
running this program.
:
Figure 4.3c : RS 232
compiling using MPLAB IDE software
The
program in figure above shows how I am able to communicate between MPLAB IDE
software to RS 232 port. I have configured all the pins in RS232 port with the
software. For this program I am using while_if method.
Figure 4.3d : UART main
compiling using MPLAB IDE software
In this figure
shows how I need to combine or interface the program of MPLAB IDE software by
using PIC 16F877A to UART that using Verilog HDL software. Verilog HDL is a
case sensitive and I must declare all the details in the program.
Figure 4.3e : UART
compiling using MPLAB IDE software
For this figure it is shown the
codings that I have to synchronize with UART peripheral device to perform the
output at the Altera DE2 board. The codings must be complete and no error so
that the output of this program can be compile with the Verilog HDL program to
perform the output of this final year project.
4.4 SUMMARY OF THE CHAPTER
In this chapter,
I have explained The Electronic Circuit Analysis and Theory, The Expected
Output and The Expected Result. I also provide the codings from both software
from the Verilog HDL and MPLAB IDE. Unfortunately, the Altera DE2 board could
not interface with this programming. There were a few problems occur while doing software and hardware on this
project. In order to solve this problems, the research and discussion were made
with supervisor and also some references from journal report.
CHAPTER
5
CONCLUSION
AND RECOMMENDATION
5.1 CONCLUSION
This review has introduced the technique
of Universal Asynchronous Receiver/ Transmitter and has demonstrated its great
potential for use in a wide range of communication. A main focus has been the
assessment of the data transmission system. In recent years there has been
interesting the technique, and driven by the demand for low cost, simple and
portable technology forth settings, the availability of low cost and small
semiconductor components, and the advancement of computer analysis techniques.
I can conclude from this project that I am trying my best to achieve my
objective. First, I success todesign a serial asynchronous receiver and
transmitter communication with standard I/O serial devices. Then, I also
success to achieve my second objective, that is design a UART that can be
prototyping Altera DE2, then testing and debugging the prototype in system. At
the same time, I also cananalyze the features of UART technology and make
comparison with other existing UART technology. In addition, I also implement
the asynchronous receiver-transmitter in Altera DE2 board to achieve fast
prototyping and design verification. Lastly, I already know how to use and
capable using UART in Verilog HDL.Here, I already achieve our entire objective.
This design uses Verilog HDL as design language to achieve the modules of UART.
Using this software, Altera’s series chip to complete simulation and test, the
result may be stable and reliable. The design has great flexibility, high
integration with some reference value. Especially in the field of electronic
design, where technology has recently become increasingly mature, this design
shows great significance. This project describes the architecture of UART that
support various data word length, parity selection and baud rates for serial
transmission of data. Working principle of this UART has been tested using
simulator, which can be implemented on Altera DE2.
Unfortunately,
this project is not successfully developed. The Altera DE2 Board is still not
been fully interface with the Universal Asynchronous Receiver / Transmitter.
Sometimes the resistor tolerance also gives effect to the circuit. When supply
the voltage, make sure it will enhance the circuit to run, not to ruin the
circuit. That is why the datasheet of every component is very important to know
the voltage and current limit.
5.2 RECOMMENDATION
Few
recommendations to upgrade the system of Universal Asynchronous Receiver /
Transmitter have been thought throughout this two semester. First, try to use FTDI
chip to interface the Altera DE2 Board and UART. FTDI chip carries the RS232
handshake signaling with the main-stream data exchange over the same USB bulk
endpoint; bulk OUT EP: TxD - RTS, DTR, bulk IN EP: RxD - CTS, DSR, DCD, RI. Then,
at least, the order of the signaling is preserved but the detailed timing is
not guaranteed. For example, when we handle serial lines on a PC application as
follows, PC sets RTS, 3 ms delay and PC sends data over TxD. On the RS232 side
of the chip, we will observe this sequence RTS change, 0 ms or more delay and
TxD starts. SiLabs and Prolific chip carries the handshake signaling over the
default endpoint, instead of the bulk one. The timing between different
endpoints is not guaranteed, even for the order. In above example, we may see
this result on the RS232 side such as TxD starts, some ms delay and RTS change.
FTDI is better, when the handshake signaling is applied. But when the
application makes the detailed timing on the PC app, it may still fail even on
FTDI chip. This argument is extended to all USB application. When we want to
guarantee the timing over USB, there is no other way than applying the USB
frame (or microframe) number to synchronize the host application and the
device. The last one is, since this project is about to do research and need to
collect data, I would like to suggest to the university to extend the period of
doing the final project.
6.0 REFERRENCES
[1] S.
Mackay, E. Wright, D. Reynders, J. Park, Practical Industrial Data Networks:Design, Installation and
Troubleshooting, Newnes, 2004ISBN 07506 5807X, pages 41-42
[2] Wilson,
Michael R. (January 2000). "TIA/EIA-422-B Overview". Application Note 1031. National
Semiconductor. Retrieved 28 July 2011
[3] Joseph
Cavanagh, Digital Design and Verilog HDL Fundamentals, Published 17th June 2008
by CRC Press
[4] D. Michael Miller;
Mitchell A. Thornton (2008). Multiple
Valued Logic: Concepts and Representations. Synthesis lectures on
digital circuits and systems. Morgan & Claypool Publishers. ISBN 978-1-59829-190-2.
[5] JanickBergerdon,
"Writing Test benches: Functional Verification of HDL Models", 2000.
[6] http://www.altera.com.my/education/univ/materials/boards/de2/unv-de2-board.html
[7] http://www.verilogcourseteam.com/vlsiproject3
[8] I. M. Braverman, “The Cutaneous Microcirculation”, J Investig Dermatol Symp
Proc. ,vol.5, pp.3-9,2000
[9] J. D. Briers, Laser Doppler and
time-varying speckle: reconciliation, J. Opt. Soc. Am. A 13 (1996), 345-50
[10] Lecture Note Digital Design S1P 2013, Sir
Suhaimi Bahisham bin Yusof, Universiti Kuala Lumpur British Malaysian
Institute.