FYP REPORT

For FYP semester 1, I need to submit the first three chapter of my FYP Report. The first chapter is Introduction. Below shows the contents needed in this chapter:

1.1 Introduction of chapter
1.2 Project Background
1.3 Project Statement
1.4 Objective
1.5 Scope of Project / Limitation
1.6 Summary of Chapter

The second chapter is Literature Review. The second chapter contents are:
2.1 History
      2.1.1 Previous Work
      2.1.2 Present Work
2.2 Review of History
2.3 Summary

Third chapter is Methodology and below are the contents needed:
3.1 Introduction
3.2 Block Diagram
      3.2.1 Explanation
3.3 Hardware & Development
3.4 Software Development
3.5 Summary

All the chapter above are still in process of making and will be submitted in this semester.

PROGRESS REPORT

To: Sir Suhaimi Bahisham Jusoh@Yusoff

From: Muhammad Fahmi bin Shamsudin  (51211210173)

Subject: Progress Report (January 15 until April 30, 2013.) Development of Universal Asynchronous Receiver/ Transmitter (UART) Interface using Verilog HDL.

Introduction:

The main goal of this engineering project is to communicate the UART with Altera DE2 board using Verlog HDL to translate data between parallel and serial forms. This proposal and designation is in conjunction with communications standards such as RS232, which interface with Verilog HDL.

Work Completed from January 15 until April 30, 2013:

I have done many researches for my Final Year Project. After discussing on the nature of the project and the objectives, I have come an understanding about the project. So the work plan had been create to guide the whole project progress.

I try to do the progress of my project as much as I could do. I have plan very details about work and task I need to do later on. I have planned to find out how the Universal Asynchronous Receiver/ Transmitter is working. In addition, I have to make some research on how do UART and Verilog HDL are interfaced in order to achieve the objectives of this project. From now, I have learned basic technique that I can apply in my project.

Problem Encountered:

          For the RS232 port and the Altera DE2 board, both of it need to be related with each other, but the work for it is still in research and the method for it also still in research so that I can use the most efficient and accurate method. The understanding of Verilog HDL for creating the UART interface with Altera DE2 is still insufficient and need some time to study, on how to use it for output display. I also have to know what kind of port will be the output serial, analog, digital or etc.

Conclusion:

There are several scopes of work for this project; study and identify on how the use of serial communications over a computer or peripheral device serial port, which is Universal Asynchronous Receiver/ Transmitter.

PRESENTATION WEEK

This is the project presentation week, for FYP semester 1. All FYP semester 1 student will be at Gemilang Hall starting 2.30 pm until 5.30 pm. Each student has two assessors to evaluate their project presentation. For my presentation, I was evaluated by two assessors, Madam Noor Hajar Hasan Basri and Madam Noor Amalia Sapiee. I will present the best as I can do without any problems and thanks a lot to our assessors by making our presentation goes smooth and easy.

PRESENTATION PREPARATION

In week 12, all FYP semester 1 student will have their project presentation at Gemilang Hall. The purpose of this presentation was to tell the assessor/evaluator about the project ideas and the objective of producing the project. As a preparation for the presentation, I need to make the presentation slides. The slides must contain the introduction of the project, problem statement, objective, project limits, the work plan and also the methodology. I made the slides and discuss with my supervisor/advisor about it. There were some correction and addition needed to be made before the presentation slides ready to be presented in front of the evaluator.

PROGRESS 8: BUDGET

Total all costing is RM400.00. All the costing and budget above are the estimation only and all the item and components are not finalize at all because there is only estimation and maybe involve with other component and other circuit or any upgrading to the project.

PROGRESS 7: WORKPLAN

The starting point of this project is the literature review and theoretical study. But, these actions are continuous as new information must be gathered from time to time in order to proceed with this project.

After having an overview of the component to include in this project, the suitable components were selected based on the scope and limitation of this project. Hardware implementations begin after the components were available. After that, the whole system was integrated for testing and optimization before the real demo and presentation to the panel of the final year project.

The time frame allocated for this research study is 12 months. It will start in January 2013 and it is projected to be completed in December 2013. The Gantt chart for the project and its milestone are shown as in Table 1.

Development of UART interface using Verilog HDL will be build to enables the community to visualize the impact and application of the proposed methods in determining the best solutions in designing it with respect to reliability and cost. This project will be presented on FYP Presentation Day.

 

Table 1

PROGRESS 6: OBJECTIVES & BENEFITS / CONTRIBUTION

OBJECTIVE

The objectives of the proposed project, Development of Universal Asynchronous Receiver/ Transmitter are;

1. To design a serial asynchronous receiver and transmitter communication with standard I/O serial devices.

2. To design a UART that can be prototyping Altera DE2, then testing and debugging the prototype in system.

3. To analyze the features of UART technology and make comparison with other existing UART technology.

4. To implement the asynchronous receiver-transmitter in Altera DE2 board to achieve fast prototyping and design verification.

5. To learn and expertise using Verilog HDL and Altera DE2.

BENEFITS / CONTRIBUTION

Based on the objectives above this device would provide some original contribution in the Development of UART interface using Verilog HDL. The main original contributions of this project can be stated briefly as follow:

Benefit/contribution for using Verilog HDL:

1. Compiled code speed and ability to create distributable EXEs and DLLs.

2. Powerful, flexible, and scalable design (open, connects to external libraries and third-party tools)

3. Easy to learn, use, maintain, and upgrade (intuitive graphical programming, using graphical constructs)

4. One tool for design, prototyping and deployment

5. Multidisciplinary use (same easy graphical programming language for different applications and domain experts in different disciplines in science and engineering)

6. Tight software-hardware integration (supports wide variety of data acquisition and embedded control devices)

7. Multicore-ready design (intrinsic parallelism) and support for different hardware acceleration technologies (DSPs, FPGAs, and GPUs as coprocessors)

8. Multiplatform (Windows, Mac OS, Linux, RTOSs)

Benefit/contribution of using Universal Asynchronous Receiver/ Transmitter:

1.       A UART  may be used  when:

     i. High speed is not required

    ii. An inexpensive communication link between two devices is required

2.       UART communication is very cheap

3.       Single wire for each direction (plus ground wire)

4.       Asynchronous because no clock signal is transmitted

5.       Relatively simple hardware

METHODOLOGY

PROCESS 5: METHODOLOGY

Figure 1: System Block Diagram

Actually Universal Asynchronous Receiver/ Transmitter receives/sends data to microprocessor/microcontroller through data bus. The remaining part of signal handling of RS-232 is done by UART for example start bit, stop bit, and parity.

          The following is the experimental set up for serial communication form. Data from UART Peripheral will be received to RS-232 Transceiver. It modifies or converts signal into format appropriate for efficient channel of transmission. Next it will implement using Verilog HDL. Verilog is a verilfication language and hence have rich capabilities for testing. PLI (Programming Language Interface) which gives the added flexibility in testing and verification for the code written in C and then to be integrated with HDL code.Hence, it will connect to DB9 connector which is physical medium through RS-232. Then it will programmed into Altera DE2 board for proof of concept.

The main features of hardware and software are as follows :

Hardware:

Interface: UART(RS232/RS422/TTL)

Data rate: 1200~115200 BPS

Power supply :3V or 6V

Receiving Current:160mA

Transmitting current:200mA(Peak current 250mA)

Standby current: 120mA

Software:

Verilog HDL, Windows.

Network Protocol: FPGAs, and GPUs as coprocessors

Working Environment Operation Temperature:-20C ~ 85C

Storage Temperature:-40C ~ 125C

The Altera DE2 Development and Education board was designed by professors, for professors. It is an ideal vehicle for learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone II 2C35 FPGA, the DE2 board is designed for university and college laboratory use. It is suitable for a wide range of exercises in courses on digital logic and computer organization, from simple tasks that illustrate fundamental concepts to advanced designs.Altera DE2 Development board as follows:

PROJECT RESEARCH AND DEVELOPMENT

PROGRESS 4 : RESEARCH ON UART IN VERILOG HDL

Abbreviation for Universal Asynchronous Receiver-Transmitter, UART is a chip used to manage computer serial ports, disk drive interrupts, screen refresh cycles, and any other device that requires timing. With a serial port transmission, the UART converts the bytes into serial bits and transmits those bits through an asynchronous transmission, stripping out the start and stop bits for each character. Below is a listing of various UART chips. The 16550 chip series is the most commonly used UART. The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data communication in the field of telecommunication. A UART is the microchip with programming that controls a computer's interface to its attached serial devices. Specifically, it provides the computer with the RS-232 Data Terminal Equipment (Data Terminal Equipment ) interface so that it can communicate to and exchange data with modems and other serial devices. More advanced UARTs provide some amount of buffer of data so that the computer and serial devices data streams remain coordinated. The most recent UART, the 16550, has a 16-byte buffer that can get filled before the computer's processor needs to handle the data. The original UART was the 8250. If you purchase an internal modem today, it probably includes a 16550 UART (although you should ask when you buy it). According to modem manufacturer robotics, external modems do not include a UART. For an older computer, we as user want to add an internal 16550 to get the most out of the external modem. Verilog is a verilfication language and hence have rich capabilities for testing. PLI (Programming Language Interface) which gives the added flexibility in testing and verification for the code written in C and then to be integrated with HDL code.Hence, it will connect to DB9 connector which is physical medium through RS-232. Then it will programmed into Altera DE2 board for proof of concept.

INTRODUCTION

PROGRESS 3: INTRODUCTION

Before I get started with this project, I had done some researches about the Universal Asynchronous Receiver/ Transmitter to get overview for more understanding.

A Universal Asynchronous Receiver/Transmitter is a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA, RS-232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable. The electric signaling levels and methods such as differential signaling are handled by a driver circuit external to the UART. A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously these devices are called USARTs (Universal Synchronous/Asynchronous Receiver/ Transmitter).

THE PROPOSAL

Making the Proposal

To meet the FYP requirement, I need to make a proposal for my project. The contains need for completing the proposal are an abstract, an introduction, the objectives, benefits, literature review, methodology, work plan and the budget. I need to complete this proposal in the prescribed time.

PROJECT TITLE

PROGRESS 2 : PROJECT TITLE

In week 2, I had a discussion with my advisor, Sir Suhaimi Bahisham bin Jusoh@Yusoff about my project title. Sir had proposed some project title to me. Finally, a title had been approved. My project entitled "Development of Universal Asynchronous Receiver/ Transmitter Using Verilog HDL" had been registered on RPS website.

FYP BRIEFING

PROGRESS 1: FINAL YEAR PROJECT BRIEFING

I am currently a 2nd semester of the 3rd year student of Bachelor Engineering Technology in Electronics in University Kuala Lumpur British Malaysian Institute. In order to complete my study, I have to take the most important module of all called Final Year Project (FYP). This module, according to the credit hour allocated in the study planner, is a mandatory to all degree students.

The first FYP briefing was held at Dewan Gemilang on 24 January 2013, we were being briefted by FYP coordinator about the methods and the flow of FYP 1 for this semester and the FYP 2 on the next semester. The main agenda during the final year project briefing are about to how to kickstart the FYP, the dateline of the title to be submit and advisor selection.