PROGRESS REPORT

To: Sir Suhaimi Bahisham Jusoh@Yusoff

From: Muhammad Fahmi bin Shamsudin  (51211210173)

Subject: Progress Report (January 15 until April 30, 2013.) Development of Universal Asynchronous Receiver/ Transmitter (UART) Interface using Verilog HDL.

Introduction:

The main goal of this engineering project is to communicate the UART with Altera DE2 board using Verlog HDL to translate data between parallel and serial forms. This proposal and designation is in conjunction with communications standards such as RS232, which interface with Verilog HDL.

Work Completed from January 15 until April 30, 2013:

I have done many researches for my Final Year Project. After discussing on the nature of the project and the objectives, I have come an understanding about the project. So the work plan had been create to guide the whole project progress.

I try to do the progress of my project as much as I could do. I have plan very details about work and task I need to do later on. I have planned to find out how the Universal Asynchronous Receiver/ Transmitter is working. In addition, I have to make some research on how do UART and Verilog HDL are interfaced in order to achieve the objectives of this project. From now, I have learned basic technique that I can apply in my project.

Problem Encountered:

          For the RS232 port and the Altera DE2 board, both of it need to be related with each other, but the work for it is still in research and the method for it also still in research so that I can use the most efficient and accurate method. The understanding of Verilog HDL for creating the UART interface with Altera DE2 is still insufficient and need some time to study, on how to use it for output display. I also have to know what kind of port will be the output serial, analog, digital or etc.

Conclusion:

There are several scopes of work for this project; study and identify on how the use of serial communications over a computer or peripheral device serial port, which is Universal Asynchronous Receiver/ Transmitter.