METHODOLOGY

PROCESS 5: METHODOLOGY

Figure 1: System Block Diagram

Actually Universal Asynchronous Receiver/ Transmitter receives/sends data to microprocessor/microcontroller through data bus. The remaining part of signal handling of RS-232 is done by UART for example start bit, stop bit, and parity.

          The following is the experimental set up for serial communication form. Data from UART Peripheral will be received to RS-232 Transceiver. It modifies or converts signal into format appropriate for efficient channel of transmission. Next it will implement using Verilog HDL. Verilog is a verilfication language and hence have rich capabilities for testing. PLI (Programming Language Interface) which gives the added flexibility in testing and verification for the code written in C and then to be integrated with HDL code.Hence, it will connect to DB9 connector which is physical medium through RS-232. Then it will programmed into Altera DE2 board for proof of concept.

The main features of hardware and software are as follows :

Hardware:

Interface: UART(RS232/RS422/TTL)

Data rate: 1200~115200 BPS

Power supply :3V or 6V

Receiving Current:160mA

Transmitting current:200mA(Peak current 250mA)

Standby current: 120mA

Software:

Verilog HDL, Windows.

Network Protocol: FPGAs, and GPUs as coprocessors

Working Environment Operation Temperature:-20C ~ 85C

Storage Temperature:-40C ~ 125C

The Altera DE2 Development and Education board was designed by professors, for professors. It is an ideal vehicle for learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone II 2C35 FPGA, the DE2 board is designed for university and college laboratory use. It is suitable for a wide range of exercises in courses on digital logic and computer organization, from simple tasks that illustrate fundamental concepts to advanced designs.Altera DE2 Development board as follows: