The starting point of this project is the
literature review and theoretical study. But, these actions are continuous as
new information must be gathered from time to time in order to proceed with
this project.
After having an overview of the component to include in this project, the suitable components were selected based on the scope and limitation of this project. Hardware implementations begin after the components were available. After that, the whole system was integrated for testing and optimization before the real demo and presentation to the panel of the final year project.
The time frame allocated
for this research study is 12 months. It will start in January 2013 and it is projected
to be completed in December 2013. The Gantt chart for the project and its
milestone are shown as in Table 1.
Development of UART
interface using Verilog HDL will be build to enables the community to visualize
the impact and application of the proposed methods in determining the best
solutions in designing it with respect to reliability and cost. This project
will be presented on FYP Presentation Day.
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| Table 1 |
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